The present invention relates to a step pulse generating circuit of a floppy disk drive installed in a system such as a personal computer, and more particularly to a circuit for generating a sub-step pulse control signal using a step pulse.
A general floppy disk drive (FDD) has a stepping circuit for generating phase variations twice when one step pulse is applied and, in this case, a second step pulse, generated in the FDD so as to produce the second phase variation, is called a sub-step pulse. A system such as a personal computer, a word processor and the like, having the FDD generates a series of step pulses for driving a stepping motor of the FDD. Then the FDD receives the step pulses and produces a final step pulse varying the phase of the stepping motor together with the sub-step pulse generated therein.
Referring to FIG. 1, a conventional step pulse generating circuit has a sub-step pulse control signal generating circuit 1, a sub-step pulse generating circuit 2 and a final step pulse generating circuit 3. Since the sub-step pulse generating circuit 2 is well known to the art, the construction thereof is omitted. The sub-step pulse control signal generating circuit 1 includes a first switch S1 connected to a power voltage Vcc through a first resistor R1 and a second switch S2 connected to a ground voltage Vss through a second resistor R2. As shown, a sub-step pulse control signal generated from the sub-step pulse control signal generating circuit 1 is determined by the switch S1 or S2 installed on a PCB (printed circuit board). If the first switch S1 is set to "ON" state, the sub-step pulse control signal of logic "high" level is produced, and if the second switch S2 is set to "ON" state, the sub-step pulse control signal of logic "low" level is generated. Thus, a pulse interval triggering a sub-step pulse produced from the sub-step pulse generating circuit 2 has no relation to a step pulse and is influenced by times t1 and t2 as shown in FIGS. 2A through 2F. The times t1 and t2 are determined by the construction of the switches S1 and S2.
FIGS. 2A to 2C show pulse waveforms when the first switch S1 is set to "ON" state. That is, the sub-step pulse control signal is in logic "high" level, and the sub-step pulse, shown in FIG. 2B, is generated with an interval of time t1. At this instance, the period ST1 of the step pulse, shown in FIG. 2A must be longer than time t1.
FIGS. 2D through 2F show pulse wave forms when the second switch S2 is set to "ON" state. Here, the sub-step pulse control signal is in logic "low" level, and the generating time of the sub-step pulse, shown in FIG. 2E, becomes t2. Further, the periods ST2 and ST3 of the step pulse, shown in FIG. 2D must be longer than time t2. Usually, the times t1 and t2 are set to 3 ms (millisecond) and 1.5 ms, respectively. Therefore, the circuit of FIG. 1 has disadvantages in that the period of the step pulse should be longer than that of the sub-step pulse. Furthermore, if the step pulse of the period ST3 is applied, the final step pulse, shown in FIG. 2D is repeated with times t2 and t3. Here, since time t3 is relatively long, the stepping motor generates a great deal of oscillation when driven, and as a result, noise occurs.